library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity testadder is
end;

architecture bench of testadder is
	component compare 
		port (a,b : in std_logic_vector (7 downto 0);
			  sel : in std_logic;
		 x1,x2,x3 : out std_logic);
	end component;

  signal a,b : std_logic_vector (7 downto 0);
  signal sel,x1,x2,x3 : std_logic;

begin
	
 a   <= "00001000" , "00000000" after 5 ns  , "00100000" after 10ns,
 		"10001000" after 15 ns  , "00000000" after 20ns, "11111111" after 25ns; 
 b   <= "00001000" , "00000010" after 5 ns  , "00000000" after 10ns,
  		"10001000" after 15 ns  , "11000000" after 20ns, "00000000" after 25ns;

 sel <= '0' , '0' after 5 ns  , '0' after 10ns ,
 '1'  after 15ns , '1' after 20 ns , '1' after 25ns; 
 
 m: compare port map (a,b,sel,x1,x2,x3);

end bench;