LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- extra package included
USE ieee.std_logic_unsigned.all;

entity test_parity_encoder is
end;

architecture bench of test_parity_encoder is
  component parity_encoder
	port (input_bus  : in std_logic_vector(3 downto 0);
	output_bus : out std_logic_vector(4 downto 0)
	);		
  end component;

  signal input_bus : std_logic_vector(3 downto 0);
  signal output_bus : std_logic_vector(4 downto 0);
  
begin   
 input_bus  <= "0000", -- even 
 "0001" after 10 ns, -- odd
 "0010" after 20 ns, -- odd
 "0011" after 30 ns, -- even
 "0100" after 40 ns, -- odd
 "0101" after 50 ns, -- even
 "0110" after 60 ns, -- even
 "0111" after 70 ns; -- odd
 
    m: parity_encoder port map (input_bus, output_bus);

end bench;